System-on-chip (SoC) integrated circuits (ICs) integrate multiple components of an electronic system into one chip, e.g., processor core(s), memory blocks, external input/output (I/O) interfaces, and power management circuits. SoCs usually include at least two different power domains operating in different frequency and voltage ranges for different components, e.g., processor core(s) (CX domain), which may utilize voltages below 1V, and external I/O pads (PX domain), which may utilize higher voltages, e.g., ˜2V.
When an SoC is initially powered up, the order in which power is applied to the different power domains may be selected to reduce power consumption in the SoC and to ensure correct functionality. If power is supplied to the power domains in an incorrect order (e.g. PX comes up before CX), severe leakage or even false communication on a channel could occur, which could potentially cause the entire system to crash.
To avoid such consequences, power-on checkers (POC) (also referred to as power-on sequencers) are used to monitor the power up sequence of the different power domains and keep the I/O circuits in expected states, e.g., tristate, in the case of an incorrect power up sequence. As used herein, “tristate” refers to a condition in which the I/O driver is not driving the pad to which it is connected HIGH and is not pulling the pad LOW, but rather placing it in a high impedance state, indicating to the corresponding pad on another IC that the state of the pad is unknown or unreliable.
Logically, the functionality of a POC circuit can be realized with a single AND gate 100 with inputs for PX 104 and the complement of CX 106, and POC output 108, as shown in FIG. 1A.
FIG. 1B is a table 102 showing the logical input/output outcomes for the AND gate 100. In the ideal scenario, POC output 108 is HIGH when PX 104 is HIGH and CX is LOW, indicating an incorrect power-up sequence. However, as described above, in practice CX typically has a significantly lower voltage than PX. As such, the CX input may not be able to completely turn off a pull-up PFET (not shown) of circuitry implementing the logical AND gate 100, which may lead to a constant leakage path from PX to ground.
To reduce the leakage, native NFETs, which have a very small threshold voltage, have been used in the AND gate implementation instead of PFETs. However, as industry is moving from planar CMOS manufacturing processes to smaller FinFET (Fin Field Effect Transistor) processes, native NFETs may not be available due to process manufacture limits.
Another drawback of the AND implementation is its lack of support for CX collapse after both PX and CX have powered up. CX collapse may occur when the core(s) in the CX domain are idle or are placed in a power-save mode, which is a feature used by many mobile applications to reduce power consumption. In such cases, it is not desirable for the AND gate to output a signal indicating an incorrect power-up sequence after CX drops to LOW (i.e., state 154 in FIG. 1B where PX=1, CX=0, and POC=1), as CX may come up and collapse multiple times during normal operation of the SoC. Also, since the AND gate is powered by PX, all devices must be thick I/O devices due to the higher voltages. The voltage of CX may be further lowered and eventually flip the POC output causing unintentional I/O state lock up in the system.